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A backside growth technique of thick porous silicon layers for the on-chip RF integrated inductor is presented. ASITIC calculation confirms that the thick porous silicon substrate (through the wafer) is a better choice to achieve high quality factor RF integrated inductors. Fabrication and characterization of the through wafer PS layer with the backside growth technique were carried out, which proved the feasibility of post-processing procedure in CMOS technology. ESEM was used to observe the morphologies of the fabricated samples. The relationships of PS growth rate as a function of current density was concluded.